cystech electronics corp. spec. no. : c708e3 issued date : 2011.12.26 revised date : page no. : 1/7 MTB40N06E3 cystek product specification n -channel enhancement mode power mosfet MTB40N06E3 bv dss 60v i d 26a r dson(typ) @v gs =10v,i d =10a 35m r dson(typ) @v gs =4.5v,i d =8a features ? low gate charge 40m ? simple drive requirement ? pb-free lead plating package equivalent circuit outline absolute maximum ratings (t c =25 c, unless otherwise noted) to-220 MTB40N06E3 g gate d drain s source g d s parameter symbol limits unit drain-source voltage v ds 60 v gs 20 v gate-source voltage i d 26 continuous drain current @ t c =25 c i d 16 continuous drain current @ t c =100c pulsed drain current *1 i dm 50 i as 26 a avalanche current avalanche energy @ l=0.1mh, i d =26a, r g =25 e as 34 repetitive avalanche energy @ l=0.05mh *2 e ar 5 mj total power dissipation @t c =25 50 p d w total power dissipation @t c =100 20 operating junction and storage temperature range tj, tstg -55~+150 c note : *1 . pulse width limited by maximum junction temperature *2. duty cycle 1%
cystech electronics corp. spec. no. : c708e3 issued date : 2011.12.26 revised date : page no. : 2/7 MTB40N06E3 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 2.5 c/w thermal resistance, junction-to-ambient, max r th,j-a 62.5 c/w characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 60 - - v v gs =0, i d =250 a v gs(th) 1.0 1.8 3.0 v v ds =v gs , i d =250 a g fs *1 - 36 - s v ds =5v, i d =10a i gss - - 100 na v gs = 20, v ds =0 - - 1 a v ds =60v, v gs =0 i dss - - 25 a v ds =60v, v gs =0, tj=125 c - 35 45 m v gs =10v, i d =10a r ds(on) *1 - 40 50 m v gs =4.5v, i d =8a dynamic qg *1, 2 - 12 - qgs *1, 2 - 3.4 - qgd *1, 2 - 3.8 - nc i d =10a, v ds =20v, v gs =10v t d(on) *1, 2 - 10 - tr *1, 2 - 3.5 - t d(off) *1, 2 - 32 - t f *1, 2 - 7.5 - ns v ds =20v, i d =1a, v gs =10v, r g =6 ciss - 1137 - coss - 47.3 - crss - 35.7 - pf v gs =0v, v ds =25v, f=1mhz source-drain diode i s *1 - - 26 i sm *3 - - 50 a v sd *1 - - 1.3 v i f =i s , v gs =0v trr - 15 - ns qrr - 8 - nc i f =5a, di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping MTB40N06E3 to-220 (pb-free lead plating package) 50 pcs / tube, 20 tubes/box, 4 boxes/carton
cystech electronics corp. spec. no. : c708e3 issued date : 2011.12.26 revised date : page no. : 3/7 MTB40N06E3 cystek product specification typical characteristics typical output characteristics 0 10 20 30 40 50 60 01234 5 brekdown voltage vs ambient temperature 50 55 60 65 70 75 80 -100 -50 0 50 100 150 200 tj, junction temperature(c) bv dss , drain-source breakdown voltage(v) v ds , drain-source voltage(v) i d , drain current(a) 10v 9v 8v 7v 6v 5v v gs =4v v gs =2v i d =250 a, v v = 3v gs =0v gs static drain-source on-state resistance vs drain current 10 100 1000 10000 0.001 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =3v v gs =2.5v v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0246810 i dr , reverse drain current(a) v sd , source-drain voltage(v) v gs =0v tj=25c static drain-source on-state resistance vs gate-source voltage 0 40 80 120 160 200 240 280 320 360 400 024681 v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) tj=150c 0 i d =10a i d =8a drain-source on-state resistance vs junction tempearture 0 20 40 60 80 100 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds(on) , static drain-source on-state resistance(m) v gs =4.5v, i d =8a v gs =10v, i d =10a
cystech electronics corp. spec. no. : c708e3 issued date : 2011.12.26 revised date : page no. : 4/7 MTB40N06E3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 1 1.2 1.4 1.6 1.8 2 2.2 2.4 -60 -20 20 60 100 140 tj, junction temperature(c) v gs( th) , threshold voltage(v) i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 0.01 0.1 1 10 drain current-id(a) g fs , forward transfer admittance(s) v ds =10v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 2 4 6 8 10 12 14 16 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =20v i d =10a maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) r ds( on) limited dc 10ms 100ms 1ms 100 10 s t c =25c, tj=150c v gs =10v single pulse maximum drain current vs case temperature 0 5 10 15 20 25 30 25 50 75 100 125 150 175 t c , case temperature(c) i d , maximum drain current(a)
cystech electronics corp. spec. no. : c708e3 issued date : 2011.12.26 revised date : page no. : 5/7 MTB40N06E3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 10 20 30 40 50 60 70 024681012 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v power derating curve 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 t c , case temperature() p d , power dissipation(w) transient thermal response curves 0.01 0.1 1 10 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) z jc (t), thermal response single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.z jc (t)=2.5 c/w max. 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *z jc (t)
cystech electronics corp. spec. no. : c708e3 issued date : 2011.12.26 revised date : page no. : 6/7 MTB40N06E3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c708e3 issued date : 2011.12.26 revised date : page no. : 7/7 MTB40N06E3 cystek product specification to-220 dimension *: typical inches millimeters inches a b e g i k m o p 3 2 1 c n h d 4 marking: 40n06 device name date code 1 2 3 3-lead to-220 plastic package cystek package code: e3 style: pin 1.gate 2.drain 3.source 4.drain millimeters dim min. max. min. max. dim min. max. min. max. a 0.2441 0.2598 6.20 6.60 i - * 0.1508 - * 3.83 b 0.3386 0.3543 8.60 9.00 k 0.0299 0.0394 0.76 1.00 c 0.1732 0.1890 4.40 4.80 m 0.0461 0.0579 1.17 1.47 d 0.0492 0.0571 1.25 1.45 n - * 0.1000 - * 2.54 e 0.0142 0.0197 0.36 0.50 o 0.5217 0.5610 13.25 14.25 g 0.3858 0.4094 9.80 10.40 p 0.5787 0.6024 14.70 15.30 h - * 0.6398 - * 16.25 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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